1. Field of the Invention
This invention relates to a modulo eight counter and more particularly to such a counter for the provision of timing signals in a digital display unit.
2. Description of the Prior Art
In order to reduce the manufacturing costs of the circuitry for a digital display unit, it is desirable to achieve as many functions on a single integrated circuit chip as permissable, either by increasing the packing density of the gates in the chip or by novel circuit designs and architecture creation. This in turn leads to wider use of the digital display units to in turn accommodate more applications for information processing systems.
Such digital display units may be custom made or may be formed of conventional commercial television sets. In either case, the information displayed is usually of the nature of characters formed of dot matrix where the display unit employs a raster scan mode. Each horizontal line is divided into a number of discrete points or areas called picture elements (PELS) or pixels. A fraction of such picture elements per line is not employed for information display but is that portion of the scan time required for horizontal retrace and synchronization of the horizontal oscillator.
As the display screen is scanned, the dot matrix characters are formed by character generation circuits that control the modulation of the electron beam (in the case of CRT displays), individual circuits of which are selected by character codes that are stored in the memory. This code store can be a shift register with exactly the same number of cells as there are character positions on the display screen, or it may be a random access memory.
In some display units, 25 to 30 complete scans of all the lines making up the display are made per second. Thus, each portion of a character being displayed is on display 25 to 30 times a second for a brief period and this can cause an apparent flickering. The flickering problem is normally solved by refreshing or redrawing all the lines in the display in two consecutive interlaced scans. A "half-scan" is redrawn or refreshed in half the time. Because of the 2:1 interlace between the two half-scans, if a horizontal line is drawn in one half-scan and is adjacent to a line drawn in the next half-scan, the two form a line on the display screen with reduced flicker because, in essence, it is written twice as often. Applying this knowledge, a 6.times.8 dot matrix character can be displayed on a 12.times.16 dot matrix, by displaying each dot in the 6.times.8 matrix four times. This reduces flicker considerably, as the character now seems to be written 50 to 60 times a second, instead of 25 to 30 times.
In modern practice, the character generation circuits and the code stores are implemented in integrated circuitry where care must be given to the number of gates and resultant capacitance involved so as to allow the circuitry to operate at very high speeds to generate the appropriate signals to drive the display. Such integrated circuitry is driven by a clock with the appropriate timing signals required for the synchronization of the respective horizontal and vertical scans and retrace being created by a counter which counts the number of time intervals required for restarting the various scans and other events.
In the past, such a counter has been a binary counter which employs a number of gates so as to make it difficult to implement for operation at very high speeds.
It is then an object of the present invention to provide an improved counter for a digital display unit.
It is another object of the present invention to provide an improved counter for a digital display unit which can be implemented with a reduced number of gates and thus reduce circuit delays.
Still another object of the present invention is to provide an improved counter that can be implemented on an integrated circuit chip for operation at very high speeds.